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International Journal of Modern Computer Science and IT Innovations

Open Access Peer Review International
Open Access

Shifting Scan Quality Left: A Hierarchical RTL-Based Verification Framework with Proven Silicon Correlation

DOI https://doi.org/10.55640/ijmcsit-v03i10-05
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Sashaank Kasturirangan 1 ,
4 Independent Researcher, USA

Abstract

The relentless pursuit of higher integration densities in the semiconductor industry, marked by the transition to sub-5nm process nodes, has pushed traditional Design for Testability (DFT) methodologies to their breaking point. As System-on-Chip (SoC) designs scale to encompass billions of transistors and hundreds of heterogeneous Intellectual Property (IP) blocks, the conventional gate-level DFT insertion and verification flow has become a primary source of schedule unpredictability and late-stage design closure failures. This report presents a comprehensive analysis of the "Shift-Left" paradigm as applied to DFT, proposing a hierarchical, Register-Transfer Level (RTL)-based verification framework. By moving DFT architectural decisions, insertion, and design-rule checking (DRC) to the RTL stage, designers can concurrently optimize for power, performance, and area (PPA) while drastically reducing the time required for Automatic Test Pattern Generation (ATPG) and physical synthesis. The research explores the mechanisms of hierarchical partitioning, core-wrapping via IEEE 1500 standards, and the integration of functional fault grading to bridge the coverage gaps inherent in structural testing. Central to this framework is the concept of silicon correlation ensuring that pre-silicon RTL-based metrics accurately reflect post-silicon yield and diagnostic results. Through an examination of industrial case studies and recent advancements in Electronic Design Automation (EDA), this report demonstrates that a hierarchical RTL-based approach provides a scalable and predictable path to achieving zero-defect quality in modern high-performance computing and automotive applications.

Keywords

Shift-Left DFT, Hierarchical Verification, RTL Scan Insertion, Silicon Correlation

References

"A Comprehensive Study on the Shift-Left Movement in the EDA Field," arXiv, 2025.
H. Woo et al., "Secure Scan Architecture Protecting Scan Test and Scan Dump," IEEE Access, vol. 9, 2021.
"A New Framework for RTL Test Points Insertion Facilitating a Shift-Left DFT Strategy," ResearchGate/IEEE, 2024.
"DFT Guide: Fault Models, Scan Insertion, and ATPG," Scribd Document.
R. Ruiz, "DFT For SoCs Is Last, First, And Everywhere In Between," SemiEngineering, 2021.
P. K. Rajanna et al., "Optimizing Integrated Circuit Testing: A Comprehensive Approach to Testability and Efficiency," IJATEE, 2025.
"Optimizing Gate-Level Simulation Performance Through Cloud-Based Distributed Computing," ResearchGate, 2024.
"Advanced Silicon Debugging and Post-Si Validation," Scribd Document.
"What is Design for Test?," Synopsys Glossary.
"Hierarchical DFT Flow Using Core-Wrapping Methodologies for Modern SoC Designs," IJCRT, 2025.
"Hierarchical Scan Test Architecture for SoC Designs," Maynooth University, 2010.
"Hierarchical DFT with Enhancements for AC Scan Test Scheduling and On-Chip Compression," IEEE Case Study.
"Design for Testability Based on Scan and ATPG Methodology," IJCI, vol. 12, no. 5, 2023.
"Developing a Hierarchical DFT Flow using Core-Wrapping Methodologies," IJCRT, 2025.
V. Boppana et al., "Hierarchical Error Diagnosis Targeting RTL Circuits," IEEE International Conference on VLSI Design, 2000.
"Test-Model Based Hierarchical DFT Synthesis," IEEE/ACM ICCAD, 2002.
"Reducing Area Overhead Introduced by Test Point Insertion," International Test Conference (ITC).
"Beyond Traditional Testing: Integrating DV and DFT for Zero-Defect Quality," DVCon India, 2025.
"Tessent Silicon Lifecycle Solutions: Enabling the Next Step in IC Test and Monitoring," Siemens EDA White Paper.
"Pre-DFT DRC for Higher QoR in Hyperscale Chips," Tessent/Siemens EDA, 2019.
"Addressing Silicon Lifecycle Scaling Demands," SemiEngineering/Siemens EDA.
"Hierarchical DFT Flow and Core-Wrapping Methodologies for SoC Testability," IJCRT, 2025.
"Detailed Silicon Correlation Results and Functional Fault Grading in Industrial Frameworks," DVCon, 2025.

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