The relentless pursuit of higher integration densities in the semiconductor industry, marked by the transition to sub-5nm process nodes, has pushed traditional Design for Testability (DFT) methodologies to their breaking point. As System-on-Chip (SoC) designs scale to encompass billions of transistors and hundreds of heterogeneous Intellectual Property (IP) blocks, the conventional gate-level DFT insertion and verification flow has become a primary source of schedule unpredictability and late-stage design closure failures. This report presents a comprehensive analysis of the "Shift-Left" paradigm as applied to DFT, proposing a hierarchical, Register-Transfer Level (RTL)-based verification framework. By moving DFT architectural decisions, insertion, and design-rule checking (DRC) to the RTL stage, designers can concurrently optimize for power, performance, and area (PPA) while drastically reducing the time required for Automatic Test Pattern Generation (ATPG) and physical synthesis. The research explores the mechanisms of hierarchical partitioning, core-wrapping via IEEE 1500 standards, and the integration of functional fault grading to bridge the coverage gaps inherent in structural testing. Central to this framework is the concept of silicon correlation ensuring that pre-silicon RTL-based metrics accurately reflect post-silicon yield and diagnostic results. Through an examination of industrial case studies and recent advancements in Electronic Design Automation (EDA), this report demonstrates that a hierarchical RTL-based approach provides a scalable and predictable path to achieving zero-defect quality in modern high-performance computing and automotive applications.